Various applications require two or more integrated circuits (ICs) or “chips” to communicate. Conventional techniques for chip-to-chip data transfer include SSTL (Stub Series Terminated Logic), LVDS (Low Voltage Differential Signaling), LVPECL (Low Voltage Positive Emitter Coupled Logic), CML (Current Mode Logic) and other differential techniques. For very high speed and throughput applications, low swing differential signaling schemes like LVDS have advantages over CMOS (Complementary Metal Oxide Semiconductor) rail-to-rail signaling in that they consume less power, produce less electromagnetic interference (EMI), and exhibit good noise immunity due to their differential signal nature.
An LVDS chip-to-chip interface uses the difference in voltage between two transmission wires to signal information. A transmitter on one chip injects a small current into one wire or the other, depending on the logic level to be sent, e.g., logic “1” or logic “0”. The current passes through a resistor at the receiving end of about 100 ohms (matched to the characteristic impedance of the transmission wires), then returns in the opposite direction along the other wire. A receiver on the other chip senses the polarity of this voltage to determine the logic level. The small amplitude of the signal and the tight electric-field and magnetic-field coupling between the two wires reduces the amount of radiated electromagnetic noise.
LVDS and the other differential techniques mentioned above are voltage mode techniques, in which the transmitted current is converted to a voltage at the receiver end to differentiate between logic “1” and logic “0”. Noise in the chip environment is mostly voltage noise, and consequently these converted voltage signals are susceptible to noise coupling. Also, high frequency effects attenuate voltage levels at the receiver end, presenting a bottom line for the minimum required voltage swing. In addition, the point at which the current-to-voltage conversion is made experiences considerable capacitance contributed by cable load, pin capacitance, bond pads, electrostatic discharge (ESD) diodes, etc. Consequently, high speed signaling slew rate (I/C) may only be maintained by increasing current, which increases power consumption.